Guides, patch notes, and application notes for power electronics design.
The boost converter's right-half-plane zero: where it comes from, why current-mode control doesn't remove it, and how a bigger inductor can leave your loop with no valid crossover frequency at all.
How to size a buck converter inductor: where the 30% ripple rule comes from, why the loss optimum is a broad basin rather than a number, and why no two manufacturers' saturation ratings mean the same thing.
Middlebrook's criterion applied to the three interfaces where stable converters combine into unstable systems: input filters, cascaded stages, and distribution buses, each with a worked example and its fix.
What component tolerance, DC bias derating, temperature and ageing do to phase margin: worst-case and Monte Carlo analysis of a buck converter loop.
Step-by-step Type III compensator design: every equation and component value for a 24V to 5V buck, rounded to standard parts and verified at 61° phase margin.
PCB layout for switching converters: find the critical high di/dt loops, minimise loop inductance, and avoid the mistakes that cause ringing and EMI.
Why voltage-mode buck converters need compensation: the LC double pole, phase margin, and what each part of a Type III compensator actually does.
The Middlebrook stability criterion compared with GMPM, ESAC, MPC, PBSC and full Nyquist on a worked 48V buck input filter, and when failing it is fine.
How to choose a MOSFET for a buck converter: why the lowest RDS(on) loses on switching losses, with worked loss calculations for high and low side.
Nine buck converter loss mechanisms behind the gap between calculated and measured efficiency: dead time, body diode, gate drive and AC winding losses.
Why power supply design still relies on disconnected spreadsheets and SPICE, and how switchmode.io connects component selection, loss and stability analysis.