Worked, not summarised.Every figure plotted.

Converter design problems taken all the way to component values, with the plots that show where the answer comes from and where it stops holding.

Fig. 1. Control-to-output gain and phase for the same buck power stage in voltage mode and in peak current mode, at 18 V input

2-part series

Current mode compensator design

Fig. 1. Peak output impedance and optimum damping resistance against n, both normalised to the characteristic impedance, with the worked example read off backwards

Input Filter Damping: Sizing Rd and Cd to an Impedance Target

Input filter damping sized from the impedance you need: the smallest Rd and Cd that hold a filter's peak under a stated limit, what the resistor dissipates, and where the tolerance goes.

stabilitylearningmulti-stage24 Sept 2026

Fig. 1. Charge against voltage for the ISC040N10NM7 output capacitance up to 48 V, showing the energy the input delivers, the part stored, and the part lost charging the rectifier

MOSFET Coss Loss in a Half-Bridge: Which Switch Pays, and How Much

MOSFET Coss loss in a hard-switched half-bridge: the switch that turns on pays its own Eoss plus Qoss x V - Eoss for the rectifier, which pays nothing. Worked from a datasheet curve.

mosfetlearninglosses21 Sept 2026

Fig. 1. Simulated switch-node ring at 65.2 MHz with nothing added, and at 33.6 MHz with a 3.3 nF capacitor added across the switch

RC Snubber Design: Sizing R and C from a Measured Ring

RC snubber design from a measured ring: find the switch node's parasitic L and C, size the capacitor against its losses, and pick the resistor that damps the ring fastest.

snubberlearninglayout18 Sept 2026

Fig. 1. Input impedance magnitude and phase for a regulated intermediate bus converter and a fixed-ratio converter at the same operating point, showing coincident magnitudes and opposite phase

Intermediate Bus Architecture: Regulated or Fixed-Ratio, and What It Costs You

Intermediate bus architecture: a regulated bus converter and an unregulated fixed-ratio one present the same input impedance magnitude, and only one of them peaks at the interface.

stabilitylearningmulti-stage8 Sept 2026

Fig. 1. Bode magnitude and phase of Type I, Type II and Type III compensators, showing that each added zero raises the phase the network can supply

Compensator Types: Choosing Between Type I, II and III

Compensator types explained: how to choose between Type I, II and III from the phase your plant has left at crossover, and why the output capacitor decides it more often than the control mode does.

compensatorlearningstability3 Sept 2026

Fig. 1. Source and load impedance vs frequency

2-part series

Input filter stability

Fig. 1. Inductor and diode current through a step increase in duty ratio, showing average diode current falling while inductor current rises

Boost Converter Right-Half-Plane Zero: Why You Can't Compensate Your Way Out

The boost converter's right-half-plane zero: where it comes from, why current-mode control doesn't remove it, and how a bigger inductor can leave your loop with no valid crossover frequency at all.

compensatorlearningboost13 Aug 2026

Fig. 1. Inductor current waveform for a 12V to 1.8V, 20A, 500kHz buck with a 0.51µH inductor

Sizing a Buck Inductor: Ripple Ratio, Saturation and the CCM/DCM Boundary

How to size a buck converter inductor: where the 30% ripple rule comes from, why the loss optimum is a broad basin rather than a number, and why no two manufacturers' saturation ratings mean the same thing.

inductorlearningbuck31 Jul 2026

Fig. 1. Source and load subsystems at an interface, with the looking-back and looking-forward impedances and the minor loop gain defined

Middlebrook's Criterion in Practice: Input Filters, Cascaded Converters, and Distribution Buses

Middlebrook's criterion applied to the three interfaces where stable converters combine into unstable systems: input filters, cascaded stages, and distribution buses, each with a worked example and its fix.

stabilitylearningmulti-stage10 Jul 2026

Fig. 1. Voltage-mode buck converter control loop

3-part series

Compensator design

Fig. 1. MOSFET turn-off ringing at different power loop inductances

PCB Layout for Switchmode Converters: The Loops That Determine Whether Your Design Works

PCB layout for switching converters: find the critical high di/dt loops, minimise loop inductance, and avoid the mistakes that cause ringing and EMI.

layoutlearning2 Jun 2026

Fig. 1. Synchronous buck converter gate drive timing at D = 0.15

Why the Lowest RDS(on) Isn't the Best MOSFET for Your Buck Converter

How to choose a MOSFET for a buck converter: why the lowest RDS(on) loses on switching losses, with worked loss calculations for high and low side.

mosfetlearningbuck27 Mar 2026

Fig. 1. Synchronous buck converter with the nine loss mechanisms covered in this article marked at their physical locations

The Buck Converter Losses Nobody Tells You About

Nine buck converter loss mechanisms behind the gap between calculated and measured efficiency: dead time, body diode, gate drive and AC winding losses.

efficiencylearningbuck13 Mar 2026

The Gap in Power Electronics Design Tools, and How We're Closing It

Why power supply design still relies on disconnected spreadsheets and SPICE, and how switchmode.io connects component selection, loss and stability analysis.

whitepaper17 Feb 2026