Every component in a switchmode converter has a datasheet but the PCB traces connecting them don't. Those traces form parasitic inductance loops that determine your voltage overshoot, your switching speed, your EMI signature, and whether your low-side MOSFET turns on when it shouldn't. No amount of component optimisation fixes a layout problem.

This article covers the three loops that matter most in a half-bridge or synchronous buck layout, with worked numbers showing exactly how much inductance causes each failure mode. The physical mechanisms are different for each loop, but the fix is the same, to minimise the enclosed area.

The worked example

48V input, 12V output, 20A, synchronous buck converter switching at 500 kHz.

Power stage components:

High-side MOSFET: 100V rated, 800 pF effective Coss at 48V operating point
Low-side MOSFET: 100V rated, 200 pF Cgd at low Vds, 2500 pF Cgs, 3V threshold voltage
Gate driver: 12V output, 0.5 Ω pull-down resistance
Input capacitance: ceramic, placed at varying distances from the MOSFETs

These values produce the conditions where layout quality separates a working converter from one that oscillates, overheats, or fails EMI.

The power loop

The power loop is the path that carries the pulsed switching current: from the input capacitor, through the high-side MOSFET, out the switch node, through the low-side MOSFET (or its body diode), and back to the input capacitor's return terminal. This current switches on and off at the switching frequency with rise times of a few nanoseconds.

The inductance of this loop resists the rapid current change. When the high-side MOSFET turns off, the load current (20A) must commutate from the channel to the low-side device. The loop inductance produces a voltage spike on the drain[1]:

$V_{peak} \approx V_{bus} + I_{load} \cdot \sqrt{\frac{L_{loop}}{C_{oss}}}$

For our 48V bus with 800 pF of effective Coss, this gives dramatically different results depending on loop inductance.

Fig. 1. MOSFET turn-off ringing at different power loop inductances.

At 2 nH (input capacitor placed directly at the MOSFET drain and source pads, tight loop on adjacent PCB layers): the drain voltage peaks at 70V. That's a comfortable 30V margin below the 100V absolute maximum.

At 5 nH (input cap within a few millimetres, reasonably tight return path): 88V. Still within spec but the margin has shrunk to 12V. Temperature derating, transient load steps, or input voltage variation could push it closer.

At 10 nH (input cap placed a centimetre or two away, typical of a layout where the controller was placed first and the power stage routed around it): 108V. This exceeds the 100V absolute maximum rating. The MOSFET is being avalanched on every switching cycle. Some devices tolerate repetitive avalanche. Many don't, and the ones that do are dissipating the clamped energy as heat that your thermal model didn't account for.

At 20 nH (input cap on the far side of the board, long traces, poor return path): 137V. The device will fail.

The ringing frequency also matters. Higher loop inductance produces lower frequency oscillation that persists longer. That ringing energy radiates from the power loop, which acts as a single-turn antenna. The radiated power is proportional to the loop area, the square of the frequency, and the square of the current amplitude. A large power loop doesn't just stress your MOSFET. It broadcasts interference across the entire switching frequency spectrum.

What the power loop actually looks like on a PCB

The schematic shows the input capacitor connected to the high-side drain and the low-side source. On the PCB, those connections are copper traces with finite width, length, and separation. The inductance of a trace depends on its geometry and, critically, on where the return current flows.

A single trace in free space has high inductance. The same trace with a return current flowing directly underneath on an adjacent layer has much lower inductance because the opposing magnetic fields partially cancel [2]. This is why the most effective power loop layouts use adjacent layers of the PCB as the forward current flows on the one layer and the return current flows directly beneath on the return layer, creating a thin, low-inductance loop.

A useful rule of thumb for PCB trace inductance is approximately 1 nH per millimetre of trace length for thin, high-aspect-ratio traces without a close return path. With a ground plane directly beneath, this drops to roughly 0.3-0.5 nH/mm depending on dielectric thickness. The difference between these two numbers is the difference between 10 nH and 3 nH for a 10 mm trace, which as Fig. 1 shows is the difference between exceeding the MOSFET voltage rating and staying safely within it.

The gate drive loop

The gate drive loop gets less attention than the power loop, but it causes a different and arguably more dangerous failure mode: parasitic shoot-through.

How shoot-through happens

When the high-side MOSFET turns on, the switch node voltage ramps from 0V to Vbus. In our example, 48V in about 4 ns which is a slew rate of 12 V/ns. This dv/dt couples through the low-side MOSFET's gate-drain capacitance Cgd and injects current into the low-side gate node [1][2].

The gate driver is supposed to be holding the low-side gate at 0V through its pull-down transistor. But that pull-down current must flow through the full gate drive loop: from the gate pin, through the source pin, along the return trace, through the driver's ground pin, through the pull-down transistor, out the driver output, along the gate trace, and back to the gate pin. The loop also includes the driver's bypass capacitor, which supplies the transient current the driver needs to sink the Miller charge.

If this loop has too much inductance, the driver's pull-down cannot respond fast enough to the injected Miller current and the gate voltage rises. If it exceeds the threshold voltage, the low-side MOSFET turns on while the high-side is already conducting. This means both switches are on simultaneously, creating a current path from Vin directly to ground limited only by the channel resistances.

Additionally, Cgd at low drain-source voltage is much higher than the value on the front page of the datasheet. The datasheet typically specifies Coss, Ciss, and Crss at 25V or 50V. But when the low-side MOSFET is off with the switch node at ground, Vds is near zero. At near-zero Vds, Cgd can be 5-10x higher than the datasheet value. A MOSFET listed at 50 pF of Crss at 25V might have 200-400 pF of Cgd at 1V. This is the capacitance that's actually coupling the dv/dt into the gate during the critical transition.

Fig. 2. Low-side gate voltage during high-side turn-on at different gate loop inductances.

With 1 nH of gate loop inductance (driver placed directly at the MOSFET, bypass cap adjacent): the gate peaks at 2.1V. Well below the 3V threshold. No shoot-through.

At 3 nH (driver close, short traces): 2.7V. Still safe but the margin is only 0.3V.

At 8 nH (driver connected via a routed PCB trace, bypass cap not immediately adjacent): 3.2V. The gate has crossed the threshold voltage. Shoot-through occurs on every switching cycle. Each event produces a current spike, additional power dissipation, and conducted EMI. The converter might still function, but it's running hotter than expected and radiating noise that wasn't in the simulation.

At 15 nH (long trace, vias in the return path): 3.3V above threshold, for 2 ns per switching cycle. At 500 kHz, that's a million shoot-through events per second.

The bypass cap is part of the gate loop

A common oversight is that the gate loop inductance isn't just the trace from driver output to MOSFET gate. The driver's Vcc bypass capacitor is part of the loop because it supplies the transient current the driver needs during switching. If the bypass cap is 5 mm away on the far side of the driver IC, those 5 mm of trace (and 5 mm of return) add roughly 10 nH to the gate loop inductance before the gate trace itself contributes anything.

Place the driver's bypass capacitor on the same side of the IC as the output pin, as close to Vcc and GND as physically possible. Then place the driver itself as close to the MOSFET gate and source pins as possible. The total gate loop is the sum of all these distances.

Why adding gate resistance isn't the right fix

A series gate resistor damps the Miller-induced ringing and reduces the gate voltage spike. At 2-5 Ω, it's often enough to keep the gate below Vth even with a mediocre layout. Many application notes recommend this approach.

The problem is that the gate resistor also slows down the switching transition. A slower turn-on means more time spent in the overlap region where both high voltage and high current are present across the MOSFET, which directly increases switching loss. You're trading shoot-through (a catastrophic failure mode) for switching loss (a thermal problem). That's a reasonable trade in a prototype, but in a production design it means you've accepted a permanent efficiency penalty to compensate for a layout that could have been done properly.

The right approach is to minimise the gate loop inductance through placement, and then use the gate resistor only for fine-tuning the switching speed to balance switching loss against EMI. The resistor should be a design choice, not a layout bandage.

Common source inductance: where the two loops interact

The power loop and the gate loop share a critical node: the MOSFET source. Any inductance in the source path is common to both loops. This shared inductance, called common source inductance (CSI), creates coupling between the power circuit and the gate circuit that affects switching behaviour in ways that neither loop analysis alone would predict [3].

During turn-on, the drain current rises through the MOSFET channel. The di/dt of this current flowing through the common source inductance develops a voltage that opposes the gate drive voltage:

$V_{CSI} = L_{CSI} \cdot \frac{dI_d}{dt}$

This voltage subtracts from the effective gate drive, slowing down the turn-on. The MOSFET spends more time in the linear region, increasing switching loss. At 20A with a 5 ns current transition through 1 nH of common source inductance, the voltage is 4V, a significant fraction of the 12V gate drive.

During turn-off, the effect reverses. The falling drain current produces a voltage that adds to the gate drive, speeding up the turn-off. The result is an asymmetry in the switching speed, turn-on is slower than expected and turn-off is faster than expected. Loss calculations that assume symmetric switching transitions will be wrong.

Kelvin source connections

Modern power MOSFETs in packages like PQFN, TOLL, and SO-8 often provide a dedicated "source sense" or "Kelvin source" pin [3]. This pin connects to the source bond wire inside the package but carries no power current. By connecting the gate driver's return to this Kelvin pin instead of the power source pin, the gate loop no longer shares inductance with the power loop.

If your MOSFET has a Kelvin source pin, use it. Connect the gate driver's ground return and the gate resistor (if used) to the Kelvin source. Connect the power path (input capacitor return, load current) to the power source pins. Mixing these connections reintroduces the common source inductance that the package designer spent silicon and pin count to eliminate.

If your MOSFET does not have a Kelvin source pin (common in D2PAK, DPAK, and older packages), minimise the shared source path length. Place the gate driver return connection as close to the MOSFET source pin as possible, before the power current path introduces additional inductance.

Switch node routing: the antenna you didn't design

The switch node is the highest dv/dt node on the board. In our example, 48V in 4 ns is 12 V/ns. Every square millimetre of copper connected to this node is a capacitive plate coupling into whatever's beneath or beside it, be it signal traces, feedback dividers, current sense lines or analogue references.

The instinct from power distribution is to use wide, generous copper pours for current-carrying capacity. At the switch node, this instinct is wrong. A large switch node copper area doesn't significantly reduce resistance (the current is flowing through the MOSFET, not distributed across the pour) but it does significantly increase the capacitive coupling area.

Keep the switch node copper as small as possible. Use just enough width to carry the inductor current without excessive heating, and minimise the total area [2]. Route sensitive analogue signals (feedback, current sense, compensation network) on the opposite side of the board or shielded by a ground plane.

If your stackup allows it, avoid running any signal traces directly beneath the switch node. The 12 V/ns dv/dt coupling through 0.2 mm of FR4 (about 0.5 pF per square millimetre) is enough to inject millivolts of noise into a high-impedance feedback node.

Component placement priority

A common layout approach is to place the controller IC first (because it has the most pins and is the "main" component), then route the power stage around it. This gets the priority backwards. The controller is a digital/mixed-signal IC whose placement is relatively flexible. The power stage has parasitic requirements measured in nanohenries that constrain placement to millimetres.

The recommended placement order:

First: input capacitors and MOSFETs. Place these as a unit, with the capacitors directly at the MOSFET drain and source pads. This defines the power loop and is the highest-priority placement on the board. Everything else routes around this.

Second: gate driver. Place it as close to the MOSFET gate and source (or Kelvin source) pins as possible, with its bypass capacitor immediately adjacent. This defines the gate loop.

Third: bootstrap capacitor. For the high-side driver, the bootstrap cap must be close to the boot and switch node pins. Its loop is less critical than the gate loop but still carries fast transient current.

Fourth: output inductor and output capacitors. The output loop carries continuous (not switched) current, so its inductance is less critical for EMI. Place for thermal management and short, wide connections.

Fifth: controller, feedback network, and compensation. These are small-signal components that should be placed away from the switch node, preferably shielded by ground planes, and routed with short, direct traces.

Last: bulk input capacitance. Electrolytics or large ceramics for low-frequency energy storage can be placed further from the MOSFETs. They handle the low-frequency current components and don't need to be in the fast switching loop.

Summary

Three loops determine whether a switchmode converter layout works:

The power loop (input cap to high-side drain to low-side source and back) controls voltage overshoot at turn-off. In our 48V, 20A example, the difference between 2 nH and 10 nH is the difference between 70V and 108V on a 100V-rated MOSFET.

The gate drive loop (driver bypass cap through driver through gate and source return) controls Miller turn-on susceptibility. 8 nH is enough to cause shoot-through in a 48V half-bridge with 12 V/ns dv/dt.

Common source inductance (shared between both loops at the MOSFET source) creates coupling that slows turn-on, speeds turn-off, and makes switching loss asymmetric. Kelvin source pins eliminate it; without them, careful routing is the only option.

The switch node copper should be minimised, not maximised. Sensitive signals should be routed away from it. And the component placement should start with the power loop and work outward, not start with the controller and hope the power stage fits around it.

None of these effects appear in a schematic simulation. They only exist on the physical PCB. A converter can have the best component selection, the best compensation design, and the best control loop, and still fail because of 10 mm of trace that nobody thought about.

References

[1] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 3rd ed. Cham, Switzerland: Springer, 2020.

[2] AN-1149 Layout Guidelines for Switching Power Supplies, Texas Instruments (originally National Semiconductor), Application Report SNVA021C, Oct. 1999, rev. Apr. 2013. Available: https://www.ti.com/lit/an/snva021c/snva021c.pdf

[3] Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters, Texas Instruments, Application Report SLPA009A, Jun. 2011, rev. Jul. 2011. Available: https://www.ti.com/lit/an/slpa009a/slpa009a.pdf