A buck converter in steady state is just a duty cycle and some passive components. The hard part is making it respond to a load transient without ringing, overshooting, or oscillating. That's the compensator's job.

Most tutorials skip straight to pole-zero placement and component formulae. This article starts earlier: what physical mechanism is trying to make your converter ring, where does it come from, and what does the compensator actually need to do about it? Understanding the problem properly makes the solution feel inevitable rather than arbitrary.

Part 2 will cover the component-level design procedure. This article builds the understanding you need to follow it.

The worked example

24V input, 5V output, 100W, voltage-mode buck converter switching at 150 kHz.

Power stage components:

Output inductor: 4.7 µH, 20 mΩ DCR
Output capacitance: 220 µF total (ceramic, multiple in parallel), 5 mΩ effective ESR
Load: 0.25 Ω (20A at 5V)
PWM modulator ramp: 2V peak-to-peak (modulator gain $F_m$ = 0.5)
Duty cycle: 20.8%

These values produce a plant with two frequencies that determine everything about the compensation problem: an LC resonant frequency at 4.95 kHz and a capacitor ESR zero at 145 kHz.

The feedback loop

Fig. 1 shows the control loop in block diagram form. The reference voltage $V_{ref}$ sets the target output. The error amplifier compares $V_{ref}$ to the sensed output (scaled by the feedback divider) and feeds the error into the compensator $G_c(s)$ . The compensator's output drives the PWM modulator $F_m$ , which converts the control voltage into a duty cycle. The duty cycle drives the power stage, and the LC filter smooths the switching waveform into the DC output.

The loop gain $T(s) = G_c(s) \cdot F_m \cdot G_{vd}(s) \cdot H(s)$ , where $G_{vd}$ is the power stage control-to-output transfer function and $H$ is the feedback divider gain. In the standard averaged model [1][6], a naturally sampled analog PWM modulator is simply a gain: $F_m = 1/V_{ramp}$ . It introduces no phase shift and no delay. Everything in this article is about understanding $G_{vd}$ and designing $G_c$ to compensate it.

Fig. 1. Voltage-mode buck converter control loop. The compensator $G_c(s)$ is the only block the designer controls. Everything else is set by the power stage components.

Close the loop without compensation and see what happens

Before designing a compensator, it helps to see why you need one. Start with the simplest possible feedback loop: a voltage divider sensing the output, a differential amplifier comparing it to a reference, and flat gain feeding the error signal into the PWM modulator. No frequency shaping. No poles or zeros. Just proportional gain.

Two problems appear immediately. First, without an integrator, the output doesn't settle to 5V. Proportional-only control always has a steady-state error inversely proportional to the loop gain: at $K_p$ = 0.3 the output settles to 3.9V; at $K_p$ = 4 it reaches 4.9V but never 5V. Second, the output rings after every transient because the phase margin is only about 20° regardless of gain.

But the severity of the ringing depends on the load. Fig. 2 shows each gain level at both full load (20A, blue) and 10% load (2A, red). At full load, the load resistance damps the LC resonance (loaded Q = 1.7), and the ringing decays within a few hundred microseconds. At 10% load, the damping drops away (Q = 17) and the picture changes.

The most revealing case is $K_p$ = 0.3 at 10% load. The ringing amplitude is modest, but it barely decays. The loop gain is so low that the feedback contributes almost no damping. The LC filter rings essentially free, limited only by the parasitic resistance of the inductor and capacitor. At $K_p$ = 4, the ringing decays faster but the amplitude is violent: the output swings from 2.7V to 8.2V around a 4.9V target on a 5V rail. That's a 5.5V peak-to-peak swing, enough to damage downstream loads or trip OVP/UVP thresholds. Even at $K_p$ = 1.5, the 10% load peaks at 8.3V.

Fig. 2. Step response of the uncompensated loop at three gain levels. Blue: full load (20A). Red: 10% load (2A). Increasing the gain reduces the DC error but doesn't fix the ringing. At light load, the LC resonance is barely damped and the ringing becomes severe at every gain setting. The compensator must provide adequate phase margin across the entire load range.

There's no proportional gain setting that solves both problems. Low gain: persistent ringing and large DC error. High gain: aggressive initial overshoot and the DC error is still not zero. The integrator fixes the DC error. The compensator zeros fix the ringing. Two different mechanisms, two different solutions, both inside the Type III compensator.

Where the ringing comes from: the LC double pole

The output filter is an energy storage system. The inductor stores energy in its magnetic field; the capacitor stores energy in its electric field. They exchange energy at a natural resonant frequency:

$f_{LC} = \frac{1}{2\pi\sqrt{LC}} = \frac{1}{2\pi\sqrt{4.7\,\mu\text{H} \times 220\,\mu\text{F}}} = 4.95\,\text{kHz}$

Below this frequency, the filter is essentially transparent. A change in duty cycle propagates through to the output with minimal delay. Above this frequency, the filter attenuates and phase-shifts the signal. The inductor's impedance ( $j\omega L$ ) grows, the capacitor's impedance ( $1/j\omega C$ ) shrinks, and the output voltage response falls behind the duty cycle change that caused it.

At and above resonance, the LC filter introduces up to -180° of phase shift. In the averaged model, the phase approaches -180° asymptotically but never quite crosses it (the ESR zero pulls it back toward -90° at high frequency). The minimum phase is -161° at around 25 kHz.

But -161° is close enough to -180° that the phase margin at any practical crossover frequency is terrible. At 15 kHz (a typical target for a 150 kHz converter), the plant phase is -158°. That leaves only 22° of phase margin. At 20 kHz, it's 19°. The plant phase sits between -158° and -161° across the entire useful bandwidth range. There's no crossover frequency where you get acceptable phase margin from the plant alone.

Fig. 3. Plant transfer function (modulator × power stage, including modulator delay)

Fig. 3. Plant transfer function ( $F_m \cdot G_{vd}$ ). The LC double pole at 4.95 kHz produces -40 dB/decade gain rolloff and drives the phase toward -180°. The ESR zero at 145 kHz pulls the phase back, so -180° is never reached. But the phase sits at -158° across the target crossover region. No crossover frequency gives acceptable phase margin without compensation.

The averaged model is accurate for crossover frequencies up to roughly $f_{sw}/5$ [1][7]. Beyond that, sampled-data effects from the switching process introduce additional phase lag that the model doesn't capture [5]. This is one reason the standard design guideline targets crossover at $f_{sw}/10$ : the model is accurate there, and the design has margin against the higher-order effects that appear at higher frequencies.

The buck is the most forgiving topology for compensation. Boost and buck-boost converters have a right-half-plane (RHP) zero in their control-to-output transfer function that imposes a hard upper limit on achievable bandwidth. The RHP zero adds phase lag that no compensator can cancel. For those topologies, the compensation problem is fundamentally harder.

The ESR zero: partial help from the capacitor

The output capacitor's equivalent series resistance creates a zero in the transfer function at:

$f_{ESR} = \frac{1}{2\pi \cdot ESR \cdot C} = \frac{1}{2\pi \times 5\,\text{m}\Omega \times 220\,\mu\text{F}} = 145\,\text{kHz}$

Above this frequency, the capacitor's impedance is dominated by its ESR rather than its capacitance. The gain rolloff slows from -40 dB/decade to -20 dB/decade, and the phase recovers toward -90°. This is what prevents the phase from reaching -180° in the averaged model.

With ceramics at low ESR, this zero sits near the switching frequency (145 kHz in our example, with 150 kHz switching). It doesn't help at the crossover frequency we're targeting (15 kHz). The compensator has to do all the phase recovery itself.

With aluminium electrolytics (ESR in the range of 10-100 mΩ), the ESR zero drops to 7-70 kHz and can significantly reduce the compensator's burden. This is one reason why some designers prefer a mix of ceramic and electrolytic capacitors on the output: the electrolytics provide the ESR zero that makes the loop easier to compensate, while the ceramics provide bulk capacitance and low impedance at high frequency.

Your capacitor selection directly affects how hard the compensator has to work. This is an interaction most component selection guides don't mention.

What the compensator needs to do

The compensator is a transfer function $G_c(s)$ in the feedback path. The total loop gain is $T(s) = G_c(s) \cdot G_{plant}(s)$ . The compensator reshapes the loop gain so that it crosses unity (0 dB) at the desired bandwidth with adequate phase margin.

In physical terms, the compensator has three jobs:

High gain at DC (the integrator). At very low frequencies, the compensator needs as much gain as possible. This ensures that any static error between the output voltage and the reference is amplified until the duty cycle corrects it fully. Without this integrator action, proportional-only control gives a steady-state error, as Fig. 2 showed. With an integrator, DC regulation is effectively perfect regardless of load.

Phase boost at crossover (the compensator zeros). The plant phase at 15 kHz is -158°. The compensator needs to add approximately 38° of phase at crossover to bring the margin up to 60°.

The compensator places two zeros near the LC resonant frequency. Each zero contributes up to +90° of phase. In our design, the zeros are at 3.2 kHz and 6.2 kHz, straddling the 4.95 kHz LC resonance. They boost the phase right where the LC poles are dragging it down.

This is the compensator's most important function. The two zeros exist specifically to counteract the phase damage from the LC filter. If the plant didn't have an LC filter (or if you were using current-mode control, which absorbs the inductor dynamics into the inner current loop), you wouldn't need two zeros. This is why voltage-mode control requires a Type III (three-pole, two-zero) compensator while current-mode can often get by with a Type II (two-pole, one-zero).

Gain rolloff above crossover (the compensator poles). Above the crossover frequency, the loop gain should fall as steeply as possible. The switching frequency ripple on the output must not modulate the duty cycle, and noise injected into the feedback path above crossover should be attenuated. High-frequency poles in the compensator ensure this. Our design places them at 75 kHz ( $f_{sw}/2$ ) and 145 kHz (at the ESR zero, to cancel the gain flattening from ESR above crossover).

Phase margin and gain margin: what the numbers mean

Two numbers describe how far a feedback loop is from oscillation.

Phase margin (PM) is the phase distance from -360° at the frequency where the loop gain crosses 0 dB. Equivalently, it's 180° plus the loop phase at the gain crossover frequency. The physical effect is directly visible on a load step response:

~65° PM: approximately 5% overshoot on the recovery, settling in a couple of cycles
~45° PM: approximately 20% overshoot, moderate ringing
~25° PM: approximately 50% overshoot, prolonged ringing

Most design guidelines specify 45° minimum, with 60° as the target. The extra margin isn't about the overshoot on a nominal design. It's about tolerance absorption: component values drift with temperature, age, and manufacturing variation. A loop designed for 60° at nominal will still have adequate margin at worst-case conditions. A loop designed for 45° might not.

Fig. 4. Load step response (10A step) at three phase margin values, all with 15 kHz bandwidth. At ~65° PM, the transient settles cleanly. At ~25° PM, the voltage rings for many cycles after the initial droop. The extra 40° of margin is the difference between a clean transient and a noisy one.

Gain margin (GM) is the amount of gain (in dB) that you could add to the loop before it oscillates, measured at the frequency where the loop phase reaches -180°. In our voltage-mode buck, the plant phase never crosses -180° in the averaged model, so the gain margin is theoretically infinite. This is consistent with the fact that no proportional gain can make the uncompensated loop oscillate (as Fig. 2 demonstrated: even at $K_p$ = 4, all three poles remain in the left half-plane).

In practice, real converters have additional sources of phase lag at high frequency: comparator propagation delay, gate driver delay, PCB layout parasitics, and sampled-data effects from the switching process. These can push the phase past -180° at frequencies above $f_{sw}/5$ , creating a finite gain margin. Keeping the crossover at $f_{sw}/10$ and ensuring the compensator rolls off gain aggressively above crossover protects against these effects without needing to model them precisely.

The Type III compensator: three poles, two zeros

The voltage-mode buck plant has a double pole (from the LC filter) and a high-frequency zero (from the ESR). To compensate it, you need:

Two zeros to recover the phase through crossover
An integrator (pole at origin) for DC accuracy
Two high-frequency poles to roll off gain above crossover

That's three poles and two zeros: a Type III compensator. The transfer function has the form:

$G_c(s) = \frac{\omega_{i}}{s} \cdot \frac{(1 + s/\omega_{z1})(1 + s/\omega_{z2})}{(1 + s/\omega_{p1})(1 + s/\omega_{p2})}$

Fig. 5. Loop gain Bode plot for the worked example. The compensator zeros at 3.2 kHz and 6.2 kHz (straddling the LC resonance) recover the phase at crossover. The compensator poles at 75 kHz and 145 kHz roll off the gain. The resulting loop gain crosses 0 dB at 15 kHz with 60° phase margin.

The loop gain magnitude crosses 0 dB with a slope of -20 dB/decade, which is the target for single-crossover stability. The compensator's zeros and poles are placed to ensure this smooth transition from the integrator's rising gain to the rolled-off gain above crossover.

Setting up the targets for Part 2

For our worked example, the design targets are:

Crossover frequency: 15 kHz (one-tenth of the switching frequency). This gives fast load transient response while keeping the loop well within the range where the averaged model is accurate.
Phase margin: ≥ 55°. Provides a clean transient response with minimal overshoot and leaves headroom for component variation.
Gain margin: The averaged model predicts infinite GM. In practice, target ≥ 12 dB by ensuring the compensator rolls off gain aggressively above crossover, providing margin against the parasitic phase lags that appear at high frequency.

The plant at 15 kHz has 3 dB of gain and -158° of phase. The compensator needs to bring the gain to 0 dB and boost the phase by 38° to achieve 60° PM. The two zeros, placed at 3.2 kHz and 6.2 kHz, provide this boost.

In Part 2, I'll walk through the zero and pole placement in detail, compute the op-amp feedback network component values, and verify the final loop gain against these targets.

References

[1] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 3rd ed. Springer, 2020, ch. 9.

[2] H. D. Venable, "The K factor: A new mathematical tool for stability analysis and synthesis," Proc. Powercon 10, San Diego, CA, 1983. [Online]. Available: https://www.venableinstruments.com/hubfs/The%20K%20Factor%20a%20New%20Mathematical%20Tool%20for%20Stability%20Analysis.pdf

[3] C. Basso, Designing Control Loops for Linear and Switching Power Supplies, Artech House, 2012.

[4] R. B. Ridley, "A new, continuous-time model for current-mode control," IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271-280, Apr. 1991.

[5] R. Ridley, A. Nace, and J. Beecroft, "Transient loop sweeps outperform small-signal models," Ridley Engineering Design Center, Article #114. [Online]. Available: https://ridleyengineering.com/design-center-ridley-engineering/41-frequency-response/321-114-transient-loop-sweeps-outperform-small-signal-models.html

[6] V. Vorpérian, "Simplified analysis of PWM converters using model of PWM switch, Part I: Continuous conduction mode," IEEE Trans. Aerosp. Electron. Syst., vol. 26, no. 3, pp. 490-496, May 1990.

[7] Texas Instruments, "Demystifying Type II and Type III Compensators Using Op-Amp and OTA for DC/DC Converters," Application Report SLVA662, Jul. 2014. [Online]. Available: https://www.ti.com/lit/an/slva662/slva662.pdf

[8] Texas Instruments, "Loop Stability Analysis of Voltage Mode Buck Regulator With Different Output Capacitor Types," Application Report SLVA301, Apr. 2008. [Online]. Available: https://www.ti.com/lit/an/slva301/slva301.pdf