Part 1 and Part 2 of this series designed a Type III compensator for a 24V-to-5V buck converter and verified it producing 61° of phase margin, 16 kHz crossover and comfortable gain margin. Those numbers describe the converter on your bench at 25°C with brand-new components at their nominal values.

Your converter does not live on your bench. It runs hot and cold, the output capacitor sheds capacitance under DC bias, every component carries a tolerance, and the whole thing ages for ten years in the field. The 61° you signed off on is the one operating point the converter almost never sees.

This article propagates real component variation through the Part 2 design. Every derating figure is built from datasheet envelopes, and every calculation is shown. The conclusion is uncomfortable: the phase margin you measure at nominal can be eaten from both ends, and the component you would never suspect (the output capacitor's dielectric) does most of the eating.

What we are actually looking at

Before the comparisons, it helps to see the loop gain itself. Fig. 1 plots three versions of the same compensated converter: the nominal design, a favourable corner, and the worst realistic corner. They are all the same circuit. Only the component values and the operating point differ.

Fig. 1. Loop gain magnitude and phase for the same converter at three points in its envelope. Nominal (navy) crosses over at 16 kHz with 61° phase margin. The favourable corner (green) is well-damped, crossing a touch earlier with 66°. The worst corner (red, Y5V dielectric at light load and high input voltage) crosses 0 dB at 118 kHz, well past $f_{sw}/5$ and beyond, and its phase has already passed −180° before crossover: the loop is unstable.

The nominal and favourable traces sit close together, both crossing near 15-16 kHz with healthy phase margin. That proximity is itself a result: across a wide swathe of good conditions, the loop hardly changes. The worst-case trace is a different animal. Its gain stays high to far higher frequencies, dragging the crossover out to 118 kHz, and the phase curve crosses −180° before the gain reaches 0 dB, which is the textbook signature of an unstable loop. The rest of this article is about understanding what moves a converter from the navy trace to the red one, and how likely that movement is.

The four mechanisms that move a component value

A capacitor marked 220µF is 220µF under one specific set of conditions. Four mechanisms will move it:

Initial tolerance. The manufacturing spread, stated on the datasheet: ±10% for a typical X7R, ±20% for a Y5V. Symmetric about nominal.

DC bias derating. Class II ceramics lose capacitance as DC voltage is applied across them, because the ferroelectric dielectric's permittivity falls with field strength. This is deterministic for a given part at a given voltage, and it is the mechanism most often forgotten during the design phase. The loss depends on how close the applied voltage sits to the rated voltage, and the only reliable figures come from a manufacturer's bias curve for the specific part [3].

Temperature. The dielectric's permittivity shifts with temperature. X7R holds ±15% across its range; Y5V swings +22% / −82% and is sharply peaked near 25°C [2].

Ageing. Class II ceramics lose capacitance logarithmically with time as the dielectric relaxes, quoted as percent per decade hour [1]. X7R ages at roughly 2.5% per decade hour (about −13% over ten years); Y5V ages at roughly 7% (about −32% over ten years) [1].

These stack multiplicatively. The effective capacitance at a worst-case corner is:

$C_{eff} = C_{nom} \times k_{tol} \times k_{bias} \times k_{temp} \times k_{age}$

The same four mechanisms apply to the inductor (tolerance, current derating, temperature, with negligible ageing) and to the compensator components (tolerance and temperature coefficient).

The output capacitor: same value, four dielectrics

The Part 2 design specified 220µF of output capacitance. That value can be built from several ceramic dielectrics but they differ enormously in how they derate. To isolate the effect, hold everything else fixed (same nominal value, same ESR, same compensator) and change only the dielectric.

The applied voltage is the 5V output. The worst-case temperature is +85°C. The four builds:

Budget: Y5V, 16V rated. The dielectric you find in a cheap converter.

$C_{eff} = 220\,\mu\text{F} \times \underbrace{0.80}_{-20\%\ \text{tol}} \times \underbrace{0.60}_{-40\%\ \text{bias}} \times \underbrace{0.18}_{+85°\text{C}} \times \underbrace{0.68}_{-32\%\ \text{age}} = 13\,\mu\text{F}$

The temperature term is the killer: at +85°C, Y5V is down 82% before any other mechanism acts. Stacked with bias, tolerance, and ageing, the "220µF" capacitor presents 13µF, 6% of its label.

Mid: X5R, 10V rated. The dielectric many consumer electronics.

$C_{eff} = 220\,\mu\text{F} \times \underbrace{0.90}_{-10\%} \times \underbrace{0.70}_{-30\%\ \text{bias}} \times \underbrace{0.91}_{+85°\text{C}} \times \underbrace{0.87}_{-13\%\ \text{age}} = 110\,\mu\text{F}$

X5R holds its temperature characteristic to ±15%, so the temperature term is 0.91 rather than 0.18. The result is 110µF, half the label. X5R's DC bias is worse than X7R's for the same case size because the higher-permittivity formulation is more voltage-sensitive, hence the −30% bias term at a 10V rating.

High: X7R, 25V rated. The sensible industrial choice.

$C_{eff} = 220\,\mu\text{F} \times 0.90 \times \underbrace{0.88}_{-12\%\ \text{bias}} \times 0.91 \times 0.87 = 138\,\mu\text{F}$

The generous voltage margin (5V on a 25V part) keeps bias derating to −12%. Result: 138µF, 63% of nominal.

Overrated: X7R, 50V rated. Deliberately over-specified.

$C_{eff} = 220\,\mu\text{F} \times 0.90 \times \underbrace{0.95}_{-5\%\ \text{bias}} \times 0.91 \times 0.87 = 149\,\mu\text{F}$

Doubling the voltage rating again only recovers another 11µF. This shows significant diminishing returns. The 50V part buys almost nothing over the 25V part, because at 5V the 25V part is already well down its bias curve's flat region.

What those capacitance losses do to the loop

The LC resonant frequency moves with the square root of capacitance:

$f_{LC} = \frac{1}{2\pi\sqrt{LC}}$

At nominal, $f_{LC}$ = 4.95 kHz. With the Y5V worst-case 13µF, it rises to 20.4 kHz, above the intended crossover. Running the full loop analysis at each worst-case capacitance:

Dielectric	C effective	% of nominal	$f_{LC}$	Crossover	Phase margin
Y5V 16V	13 µF	6%	20.4 kHz	102 kHz	22.7°
X5R 10V	110 µF	50%	7.0 kHz	27.5 kHz	59.4°
X7R 25V	138 µF	63%	6.3 kHz	22.9 kHz	61.2°
X7R 50V	149 µF	68%	6.0 kHz	21.6 kHz	61.5°

Fig. 2. Worst-case phase margin and crossover frequency for four ceramic dielectrics, same nominal 220µF. Three of the four hold above 59°. The Y5V build collapses to 23° and its crossover blows past $f_{sw}/5$ to 102 kHz, where the averaged model no longer applies and switching noise feeds through.

The three reasonable dielectrics (X5R and both X7Rs) barely move the phase margin despite losing 30-50% of their capacitance. This is the self-compensating behaviour: as C falls, both the LC pole and the crossover frequency rise together, and the compensator zeros keep providing their boost relative to the new crossover. Phase margin holds up well against capacitance loss, as long as the loss is moderate.

However, the Y5V is not a moderate loss. At 6% of nominal, the crossover has left the region where any of the Part 1 and Part 2 reasoning holds. The 23° phase margin is almost beside the point; a converter crossing over at 102 kHz on a 150 kHz switcher is not a working design.

The operating space: where the margin and the crossover actually live

Everything so far fixed the operating point at full load with a 24V input and varied the components. But a converter moves through a two-dimensional operating space, in this case the input voltage ranges from 18V to 30V and load current from 2A to 20A. The phase margin and crossover are surfaces over that plane, not single numbers. Fig. 3 maps both, for the sensible X7R 25V build at its worst-case capacitance.

Fig. 3. Phase margin (left) and crossover frequency (right) across the input-voltage and load-current operating space, for the X7R 25V build at worst-case capacitance. The two metrics are governed by orthogonal axes: phase margin contours run vertical (set by load), crossover contours run horizontal (set by input voltage).

The interesting feature is that the two metrics are controlled by different axes. The phase margin contours run almost vertically being set by load current and barely touched by input voltage. The crossover contours run almost horizontally being set by input voltage and barely touched by load. The two concerns decouple.

Load current sets the phase margin. The output filter's resonance is damped by the load. The quality factor of the LC pole is set by how heavily the converter is loaded:

$Q \approx \left(\frac{Z_0}{R_{load}} + \frac{ESR + DCR}{Z_0}\right)^{-1}, \qquad Z_0 = \sqrt{\frac{L}{C}}$

At full load the loaded Q is about 1.3; at light load (10%) it rises to about 4.4. A higher-Q resonance has a sharper phase transition through $f_{LC}$ , and the compensator zeros (placed for the full-load profile) recover less of it. The phase margin falls from 61° at full load to 50° at light load, an 11° erosion that has nothing to do with tolerance and everything to do with where the converter is operating. This is why light load, not full load, is the worst case for stability: a lightly-loaded converter is a lightly-damped one.

Input voltage sets the crossover. Our modulator is a fixed gain $F_m = 0.5$ , so the plant DC gain scales directly with input voltage ( $F_m V_{in}$ ). Raising $V_{in}$ from 24V to 30V raises the loop gain, which pushes the crossover from 23 kHz to 27 kHz. The phase margin barely moves (the loop shape is unchanged, it just crosses 0 dB at a higher frequency where the compensated phase is similar). A buck with input-voltage feedforward cancels this by making $F_m$ inversely proportional to $V_{in}$ ; our design does not have it, so the input range is a first-order crossover-mover. The same applies to any drift in the modulator ramp amplitude: it is a gain term, so it moves the crossover, not the margin.

The worst-case operating corner is where the two bad edges meet: high input voltage and light load, giving 49° phase margin at a 27.7 kHz crossover. That is the honest worst case for this build, and it combines an operating point (light load), a gain term (high $V_{in}$ ), and the worst-case capacitance already baked in. None of the three is visible from a single bench measurement at 24V and full load.

ESR: a zero too high to matter, here

The output capacitor's ESR sets a zero in the loop, and that zero provides phase lead, so it is reasonable to ask whether ESR variation is a hidden lever. For this ceramic design, it is not.

The ESR zero sits at $f_{ESR} = 1/(2\pi \cdot ESR \cdot C)$ . With 5mΩ and 220µF, that is 145 kHz, a decade above crossover. Varying ESR across the realistic ceramic range of 3 to 10 mΩ moves the phase margin from 58° to 68°, but almost all of that excursion is upward: more ESR means a lower zero, more phase lead, higher margin. The worst case is low ESR (3mΩ), which costs only 2.7° relative to nominal. The cold-temperature ESR rise (roughly ×1.4 at −40°C) moves the zero down and adds about 2° of margin, so cold ESR is a tailwind, not a risk.

ESR is a minor, mostly benign lever for a low-ESR ceramic design only because its zero sits far above crossover. With a higher-ESR technology (polymer or electrolytic) the zero moves toward the crossover region and ESR becomes a first-order term, which is one reason a compensator designed for ceramics cannot be dropped onto an electrolytic output without redesign. Within the all-ceramic scope of this article, ESR stays out of the way.

The inductor: a smaller lever than you would think

The inductor carries its own tolerance, current derating, and temperature drift, and the choice of core material and sizing margin changes all three. A ferrite core run close to its saturation knee sags more under load and drifts more with temperature than an oversized composite-core part.

Build	Worst-case L	Crossover	Phase margin
Ferrite, just-enough	3.1 µH	22.6 kHz	61.4°
Ferrite, oversized	3.7 µH	19.5 kHz	61.6°
Composite, just-enough	3.7 µH	19.5 kHz	61.6°
Composite, oversized	4.0 µH	18.1 kHz	61.5°

The phase margin barely moves with every cell landing within half a degree of 61°. The inductance affects the crossover frequency (the wider tolerance ferrite just-enough build wanders up to 22.6 kHz) and it strongly affects efficiency and ripple, but for the stability margin it is a second-order lever. Inductor sizing and core material are efficiency and crossover-stability decisions, not phase-margin decisions.

(The DCR of the inductor was held at nominal throughout. Checked separately across its thermal range of 17 to 26 mΩ, it moves the phase margin by under 1.5°, adding a little damping when hot. It is immaterial to the result.)

The compensator components: where not to spend money

The compensator itself is built from three resistors and three capacitors. It is tempting to reach for precision parts here, on the reasoning that the compensator sets the loop shape. The data does not support it. Varying all six compensator components to their worst-case corners, including temperature coefficient over a 60°C swing:

Compensator grade	Phase margin span
Thin film + C0G (0.1% R, 5% C)	1.0°
Thick film + X7R (1% R, 10% C)	2.5°
Worst cheap (5% R, 20% C)	6.9°

Fig. 4. Left: the inductor 2×2, phase margin essentially constant. Right: compensator-component quality, with the output-capacitor tier difference shown for scale. Even genuinely poor compensator parts move the margin less than the output-cap choice.

Thin-film and C0G versus thick-film and X7R is a 1.5° difference. Even genuinely poor compensator parts (5% resistors, 20% capacitors) move the phase margin by under 7°, less than the output capacitor dielectric choice (around 10° at full load, more at light load) and less than the light-load operating-point erosion.

The whole picture at once: every lever, swept together

Each section so far isolated one effect by freezing the others. That is how you attribute cause, but it is not how a converter is built. A real production run varies everything at once: the output capacitor's tolerance and derating, the inductor's tolerance and current sag, the ESR, the DCR, all three compensator resistors with their tolerance and temperature coefficient, all three compensator capacitors, the input voltage anywhere in its range, and the load anywhere in its range. The honest question is what the phase margin distribution looks like with all of that turned on together.

The Monte Carlo in Fig. 5 does this. Each of the 6000 runs per build tier draws every component from its distribution (operating temperature mapped through the relevant dielectric curve, tolerances uniform within band, compensator tempco over a 60°C swing) and places the converter at a random point in the 18-30V by 2-20A operating space. The build tiers are defined across the whole bill of materials, not just the capacitor: the Budget tier pairs the Y5V output cap with 5% resistors and 20% compensator capacitors; the High tier pairs the X7R 25V output cap with 0.1% thin-film resistors and 5% C0G.

Fig. 5. Full Monte Carlo phase margin distribution (6000 runs per tier), every component and the operating point sampled together. The Budget build puts 54% of the population below the 45° guideline; the Mid and High builds stay above it almost entirely.

Build tier	PM mean	PM std	PM 1st percentile	Fraction below 45°
Budget (Y5V, 5% R, 20% C)	41.4°	12.3°	4.4°	54%
Mid (X5R, 1% R, 10% C)	55.0°	3.8°	46.8°	0.1%
High (X7R 25V, 0.1% R, 5% C)	57.0°	3.3°	50.6°	0%

The result is more severe than any single section implied. The output-cap worst-case analysis put the Budget Y5V build at 23° at one corner; the operating-space map showed light load eroding another 11°; the full Monte Carlo, combining the dielectric, the operating space, and every other lever, puts 54% of Budget builds below the 45° phase-margin guideline, with the worst tail reaching into instability. More than half of that cheap converter's production, somewhere in its operating envelope, is out of specification.

The Mid and High builds tell the opposite story. Even with everything varying at once, they hold: the Mid build breaches 45° in one run in a thousand, the High build never. The difference between 54% and zero is almost entirely the output-capacitor dielectric and the operating-space penalty, not the compensator parts, which is the same conclusion the isolation sections reached, now confirmed in combination.

Notice also that the means for the good builds (55° and 57°) sit below their nominal 61°. The full spread does not centre on the bench measurement; it centres several degrees lower, because every sample carries the light-load and input-voltage penalties that the nominal point does not. The number you measure at 24V and full load is not the centre of your distribution. It is the optimistic edge of it.

What this means for how you design

The nominal analysis in Part 1 and Part 2 is necessary but it is not sufficient. The 61° it produces is a single point in a space the converter moves through constantly. In this design:

The output-capacitor dielectric is the dominant tolerance variable. A defensible X7R at a sensible voltage rating holds the worst-case margin near 60°; a Y5V budget part puts over half of production below the stability guideline once the operating space is included.
Phase margin is self-compensating against moderate capacitance loss but not against severe loss, and the crossover frequency wanders far more than the margin does, toward the region where the model itself stops being valid.
The operating point matters as much as the components. Phase margin is set by load current (light load is the worst case, eroding around 11°), and crossover is set by input voltage (the 18-30V range moves it by a third). The two decouple onto orthogonal axes, and the worst case sits where the bad edges of both meet.
The inductor, the ESR, and the compensator components, the parts engineers often fuss over, are mostly second-order for stability if reasonable choices are made.

None of this is visible from a bench measurement at nominal, and none of it is reliably predictable by inspection, because the dominant interactions are counter-intuitive: the capacitor you would never suspect dominates, the components you would tune barely matter, the worst operating point is the one with the least load, and the input voltage moves a different metric than the load does. The only way to know your worst-case margin is to propagate every variation through the loop, across the whole operating space, with the real derating envelopes attached to each part, which is what produced the 54% figure above and what no amount of bench measurement at nominal would have revealed.

That propagation, done automatically from the component library with the derating curves built in, the operating space swept, and the worst-case and statistical views side by side, is exactly what switchmode.io is being built to do. The nominal design is where you start. The worst-case envelope is where you find out whether you have a product.

References

[1] Johanson Dielectrics, "Ceramic Capacitor Aging Made Simple." [Online]. Available: https://www.johansondielectrics.com/tech-notes/ceramic-capacitor-aging-made-simple/

[2] Specap, "Ceramic Capacitor Dielectrics: Class 1 vs Class 2 (C0G, X7R, Y5V)." [Online]. Available: https://www.specap.com/resources/blog/ceramic-capacitors-class-1-vs-class-2-c0g-x7r

[3] Murata, "SimSurfing" capacitor characteristic viewer (DC bias and temperature curves by part number). [Online]. Available: https://ds.murata.co.jp/simsurfing/