Part 1 showed what a peak current loop does to a buck converter's plant. The LC resonance goes, a single pole at 727Hz takes its place, and the phase at a 50kHz crossover is −95° instead of −170°. That puts the job within reach of a Type II compensator: an integrator, one zero and one high-frequency pole.

This article turns Part 1's targets into component values, twice over. Once around an op-amp, which is how a Type II is usually drawn. Once around a transconductance amplifier, which is what most current-mode controllers actually have. The targets are the same, and the arithmetic isn't. With a transconductance amplifier, the feedback divider lands inside the loop gain.

Design targets (from Part 1)

A 9–36V to 5V, 2A buck at 500kHz, peak current mode, designed at 18V. From Part 1, the plant at 50kHz is −3.76dB and −95.2°.

The compensator targets:

Crossover frequency $f_c$ : 50kHz, a tenth of the switching frequency
Phase margin: 60° at 18V
Phase boost at crossover: 65.2°
Zero: $f_z$ = 10.98kHz
High-frequency pole: $f_p$ = 227.7kHz
Compensator gain at crossover, $v_c/v_o$ : +3.76dB, a factor of $G$ = 1.542, so that the loop gain is 0dB there
Feedback divider: 10.5kΩ over 2.00kΩ, both E96 values, giving 5.000V from a 0.8V reference

The zero and pole sit a factor of $k$ = 4.55 either side of crossover, so $f_z f_p = f_c^2$ . That symmetric placement gives the most phase boost for a given spacing [3], and it simplifies the arithmetic below.

Two ways to build a Type II

Fig. 1 shows both circuits. The component names follow TI's SLVA662 [1]: $R_1$ and $R_4$ are the divider, $R_2$ and $C_1$ set the zero, and $C_3$ sets the high-frequency pole.

Fig. 1. Type II compensator around an op-amp, with the network between COMP and FB, and around a transconductance amplifier, with the network from COMP to ground — Fig. 1. The same Type II network, $R_2$ and $C_1$ in series with $C_3$ across them, placed two ways. Left: in the feedback path of an op-amp. Right: from the output of a transconductance amplifier to ground.

Around an op-amp, the network sits between COMP and the inverting input. Feedback holds the inverting input at the reference, so it's a virtual ground. $R_4$ sets the DC output voltage and drops out of the AC analysis entirely. The compensator is the network impedance over the upper divider resistor:

H(s) = \frac{Z(s)}{R_1}

where $H(s)$ is the compensator's gain from the output voltage to the control voltage. $Z(s)$ is the impedance of the network in the feedback path, in ohms, and $R_1$ is the upper divider resistor.

Around a transconductance amplifier (OTA), there is no local feedback. The amplifier turns its input voltage into a current, and the network to ground turns that current back into the control voltage. With no virtual ground, the divider ratio and the transconductance $g_m$ both land in the gain [1, Eq. 12]:

H(s) = \frac{R_4}{R_1 + R_4}\, g_m\, Z(s)

where $R_4$ is the lower divider resistor and $g_m$ is the amplifier's transconductance, in siemens. $H(s)$ , $Z(s)$ and $R_1$ are as above.

In both cases the network is the same:

Z(s) = \frac{1 + s R_2 C_1}{s\,(C_1 + C_3)\left(1 + s R_2 \frac{C_1 C_3}{C_1 + C_3}\right)}

where:

$s$ is the complex frequency, in radians per second
$R_2$ is the resistor in series with $C_1$ , in ohms
$C_1$ is the capacitor that sets the zero with $R_2$ , in farads
$C_3$ is the capacitor across that branch, which sets the high-frequency pole, in farads

Feature	Frequency	Set by
Zero	$f_z = \dfrac{1}{2\pi R_2 C_1}$	$R_2$ , $C_1$
High-frequency pole	$f_p = \dfrac{C_1 + C_3}{2\pi R_2 C_1 C_3}$	$R_2$ , $C_1$ , $C_3$
Integrator	$\dfrac{1}{s\,(C_1 + C_3)}$ , scaled by $1/R_1$ or by $g_m R_4/(R_1+R_4)$	$C_1$ , $C_3$

The design equations

The zero and the pole fix the ratio of the two capacitors. Divide $f_p$ by $f_z$ and $R_2$ cancels:

\frac{C_3}{C_1} = \frac{f_z}{f_p - f_z}

where $f_z$ is the zero frequency and $f_p$ the high-frequency pole, both in hertz, and both taken from the targets above.

The gain at crossover fixes $R_2$ . Write the network's magnitude at $f_c$ with two correction terms, $a = \sqrt{1 + (f_c/f_p)^2}$ for the pole and $b = \sqrt{1 + (f_z/f_c)^2}$ for the zero. With symmetric placement $f_c/f_p = f_z/f_c$ , so $a = b$ = 1.024 and they cancel. Then for the op-amp:

R_2 = G\,R_1 \frac{f_p}{f_p - f_z} \cdot \frac{a}{b}

where $G$ is the compensator gain needed at crossover, 1.542 here, and $f_c$ is the crossover frequency. $a$ and $b$ are the two correction terms defined above, and $R_1$ , $f_z$ and $f_p$ are as before.

And for the OTA [1, Eq. 18]:

R_2 = G\,\frac{R_1 + R_4}{R_4\, g_m} \cdot \frac{f_p}{f_p - f_z} \cdot \frac{a}{b}

where $R_1$ and $R_4$ are the divider resistors and $g_m$ the transconductance. $G$ , $f_z$ , $f_p$ , $a$ and $b$ are as above.

The two differ only in what stands in for $R_1$ . In the OTA it is $(R_1 + R_4)/(R_4 g_m)$ . SLVA662 gives the OTA form directly. Its op-amp section is parameterised differently, so I derived the op-amp expression above and checked it numerically. Everything after that is shared:

C_1 = \frac{1}{2\pi f_z R_2} \qquad C_3 = C_1 \frac{f_z}{f_p - f_z}

where $R_2$ is the value just calculated, in ohms, and $C_1$ and $C_3$ come out in farads.

Worked example: the op-amp version

Step 1: $R_1$ = 10.5kΩ. It's the upper divider resistor, chosen with $R_4$ to set 5V. In an op-amp design it also sets the compensator's gain, so change the output voltage with $R_4$ , not $R_1$ [1].

Step 2: $R_2$ .

R_2 = 1.542 \times 10.5\,\text{k}\Omega \times \frac{227.7}{227.7 - 10.98} = 17.02\,\text{k}\Omega

Step 3: $C_1$ and $C_3$ .

C_1 = \frac{1}{2\pi \times 10{,}980 \times 17{,}020} = 851.9\,\text{pF} \qquad C_3 = 851.9\,\text{pF} \times \frac{10.98}{216.7} = 43.16\,\text{pF}

Worked example: the transconductance version

Step 1: $g_m$ = 350µS. That is the TPS54360B's typical figure [2]. Take it from your own controller's datasheet.

Step 2: $R_2$ . The divider ratio $R_4/(R_1+R_4)$ is 0.16, so $(R_1+R_4)/(R_4 g_m)$ = 17.86kΩ:

R_2 = 1.542 \times 17.86\,\text{k}\Omega \times \frac{227.7}{227.7 - 10.98} = 28.94\,\text{k}\Omega

Step 3: $C_1$ and $C_3$ .

C_1 = \frac{1}{2\pi \times 10{,}980 \times 28{,}940} = 500.9\,\text{pF} \qquad C_3 = 500.9\,\text{pF} \times \frac{10.98}{216.7} = 25.38\,\text{pF}

I checked both networks by evaluating the circuits themselves rather than the formulas above. Each one lands on Part 1's targets: 50.0kHz crossover, 60.0° of phase margin at 18V.

Rounding to standard values

E96 resistors and E12 capacitors:

Component	Op-amp exact	Op-amp standard	OTA exact	OTA standard
$R_2$	17.02kΩ	16.9kΩ	28.94kΩ	28.7kΩ
$C_1$	851.9pF	820pF	500.9pF	470pF
$C_3$	43.16pF	47pF	25.38pF	27pF

The resistors barely move. The capacitors do the damage, and they do it in the unhelpful direction. $C_1$ rounds down, which raises the zero. $C_3$ rounds up, which lowers the pole. On the OTA version the zero moves from 10.98kHz to 11.80kHz and the pole from 227.7kHz to 217.2kHz. The spacing $k$ shrinks from 4.55 to 4.29, and the boost falls from 65.2° to 63.8°.

That costs 1.3° of phase margin at every input voltage. I expected rounding to be free here, because the Type III in the voltage-mode Part 2 came out a degree better after rounding. It doesn't work that way. In that design the errors pulled against each other. Here both capacitors move the zero and the pole the same way.

It isn't a large loss, and it is avoidable. With E24 capacitors, 510pF and 24pF, the OTA version lands at 60.8° at 18V. The op-amp version takes 820pF and 43pF and lands at 59.6°. E24 values are easy to buy in C0G, the dielectric you want here anyway.

Verification

Fig. 2 shows the E12 networks on Ridley's plant at 18V.

Fig. 2. Plant, compensator and loop gain at 18 V with standard component values, for the transconductance and op-amp versions of the Type II — Fig. 2. Standard values at 18V. The compensator (red) falls at 20dB per decade from its integrator, flattens from the zero at 11.8kHz, and falls again above the pole at 217kHz. The loop gain crosses at 49.4kHz with 58.6° of phase margin. The op-amp version (dashed) lies on top of the OTA version, as it should.

At all three input corners, with E12 values:

	9V	18V	36V
Op-amp: crossover, PM, GM	49.9kHz, 61.8°, 13.8dB	49.3kHz, 58.7°, 15.3dB	49.0kHz, 57.2°, 15.9dB
OTA: crossover, PM, GM	50.0kHz, 61.7°, 13.8dB	49.4kHz, 58.6°, 15.3dB	49.0kHz, 57.1°, 15.9dB

The crossover moves by 1kHz across a 4:1 input range, which is the current-mode property Part 1 set out. The gain margin comes from the sampling pole at half the switching frequency, which is where the loop phase finally passes −180°.

Two things an OTA does that an op-amp doesn't

The divider is in the loop. Change the output voltage with the op-amp design by changing $R_4$ , and the compensator's gain at crossover doesn't move. Do the same with the OTA design and it does. Moving this converter to 3.3V takes $R_4$ from 2.00kΩ to 3.36kΩ. The op-amp's gain at 50kHz stays at 1.52. The OTA's rises to 2.31, 3.6dB more, because the divider now passes a bigger fraction of the output to the amplifier.

SLVA662 puts it plainly: with an OTA, "only the ratio of the feedback resistors is important" [1, p. 3]. That also means the ratio is part of your compensation. Change the output voltage on an OTA design and redo $R_2$ .

$g_m$ is a gain you don't control. In the op-amp version, the gain is a ratio of two resistors you chose. In the OTA version it is proportional to $g_m$ , which is set inside the chip. The TPS54360B datasheet gives a typical value only [2]. If $g_m$ is 20% off, on the standard-value OTA network at 18V:

$g_m$	Crossover	Phase margin	Gain margin
280µS (−20%)	40.1kHz	59.4°	17.2dB
350µS	49.4kHz	58.6°	15.3dB
420µS (+20%)	58.6kHz	57.0°	13.7dB

The phase margin barely moves, because the plant phase is flat near crossover. The crossover does move, and with it the load-step response. Check your part's $g_m$ limits before you promise a transient spec.

The OTA's finite gain matters much less. The TPS54360B's 10,000V/V turns the ideal integrator into a pole at 11Hz, far below anything that affects the margins.

What comes next

Every number here assumes the compensating ramp that Part 1 chose, 0.67 times the inductor downslope, without justifying it. Part 3 is about that choice. It covers how much ramp a peak current-mode buck needs, and what too little and too much cost. It also explains why the margins in the table above still drift across the input range.

The algebra above is the easy part, and it is the part every application note covers. What costs time on a real design is everything after it. Round to the parts you can buy, re-grade at every input corner, then do it again when the inductor or the controller changes. That is the part switchmode.io automates.

References

[1] S. W. Lee, "Demystifying Type II and Type III Compensators Using Op-Amp and OTA for DC/DC Converters," Texas Instruments, Application Report SLVA662, Jul. 2014. [Online]. Available: https://www.ti.com/lit/an/slva662/slva662.pdf

[2] Texas Instruments, "TPS54360B 4.5-V to 60-V Input, 3.5-A Step-Down DC-DC Converter," SNVSB93, Dec. 2018. [Online]. Available: https://www.ti.com/lit/ds/symlink/tps54360b.pdf

[3] H. D. Venable, "The K factor: A new mathematical tool for stability analysis and synthesis," Proc. Powercon 10, San Diego, CA, 1983. [Online]. Available: https://www.venableinstruments.com/hubfs/The%20K%20Factor%20a%20New%20Mathematical%20Tool%20for%20Stability%20Analysis.pdf