Middlebrook's Criterion in Practice: Input Filters, Cascaded Converters, and Distribution Buses

Two converters can each be unconditionally stable on the bench and then oscillate the moment you connect them together. The mechanism behind this, impedance interaction at the interface, was formalised by R. D. Middlebrook in 1976 for the input-filter case [1]. But the same criterion applies wherever regulated stages share an interface. This includes cascaded converters and distribution buses feeding many point-of-load regulators.

This article works through Middlebrook's criterion with a concrete numerical example for each of those three scenarios, showing what the source output impedance and load input impedance actually look like, where they collide, and how to fix each case. If you want a broader comparison of interface stability techniques (GMPM, opposing argument, ESAC and friends), see Part 1 of our input filter stability series. Here we stay on Middlebrook and how to apply it.

The core idea: minor loop gain

Take any interface in a power system and split it into a source subsystem (everything upstream, characterised by its output impedance $Z_o$) and a load subsystem (everything downstream, characterised by its input impedance $Z_{in}$). Fig. 1 shows the arrangement.

Fig. 1. Any interface splits the system into a source subsystem with output impedance $Z_o$ and a load subsystem with input impedance $Z_{in}$. Each is stable in isolation; the stability of the interconnection is governed by the minor loop gain $T_m = Z_o / Z_{in}$.

If each subsystem is stable on its own, the interconnected system's stability is governed entirely by the minor loop gain:

$T_m(s) = \frac{Z_o(s)}{Z_{in}(s)}$

The interconnection is stable if and only if $T_m$ satisfies the Nyquist criterion: no encirclements of $-1$. Loading one stable system with another inserts $1/(1+T_m)$ into the transfer functions at the interface, and that term is where the trouble lives.

Why a regulated converter fights back

The reason this matters at all is that a regulated converter does not look like a resistor from its input terminals. Within its control bandwidth it holds output power constant, so if the input voltage dips, the input current rises. Differentiate $P_{in} = V_{in} I_{in} = \text{const}$ and you get an incremental input resistance of:

$R_N = -\frac{V_{in}^2}{P_{in}}$

Negative. A converter drawing 30W from a 24V rail presents roughly $-19\,\Omega$ to whatever feeds it. That negative resistance can undamp any resonance it sees looking back into the source, whether that's an input filter or an upstream converter's output stage, and turn a well-behaved LC into an oscillator.

Middlebrook's answer

Middlebrook's original criterion sidesteps the Nyquist plot entirely: if

$|Z_o(j\omega)| \ll |Z_{in}(j\omega)| \quad \text{for all } \omega$

then $|T_m| \ll 1$ everywhere, $T_m$ can never reach $-1$ regardless of phase, and stability is guaranteed unconditionally. In practice "much less than" becomes a design margin, commonly 6 dB, i.e. $|T_m| < 0.5$. On the complex plane this confines $T_m$ to a disc around the origin; everything outside that disc is the forbidden region (Fig. 2).

Fig. 2. The Middlebrook forbidden region. Keeping $|T_m|$ inside the teal disc of radius $1/\mathrm{GM}$ (0.5 for a 6 dB margin) guarantees the locus can never reach $-1 + j0$, whatever its phase does. Everything outside the disc is forbidden. The dashed unit circle is shown for reference.

The criterion needs only magnitude information (two impedance plots on the same axes) and it makes the fix obvious: push $|Z_o|$ down, or push the impedances apart in frequency. Its known weakness is conservatism. It prohibits many perfectly stable designs because it ignores phase entirely, and less conservative criteria such as Gain Margin–Phase Margin (GMPM) shrink the forbidden region to a wedge around the $-1$ point. Those are worth knowing when a Middlebrook-compliant design would be prohibitively expensive. For the majority of designs, though, meeting Middlebrook with 6 dB margin is cheap and needs no phase measurement, and the margin holds up as component values drift with temperature and tolerance. That's the approach I take in all three scenarios below.

The input filter: the classic case

This is the problem Middlebrook originally solved. A 24V rail feeds a 5V / 5A buck through an EMI filter (Fig. 3). At 88% efficiency, $P_{in} \approx 28.4$W, so:

$R_N = -\frac{24^2}{28.4} \approx -20\,\Omega$

The filter is a single LC stage: $L_f = 10\,\mu\text{H}$ (DCR 10mΩ), $C_f = 22\,\mu\text{F}$ ceramic (ESR 3mΩ).

Fig. 3. The 10µH / 22µF input filter feeding the 5V / 5A buck. The $R_d$–$C_d$ damping branch (dashed) is the fix developed below; the interface where $Z_o$ and $Z_{in}$ are evaluated is marked.

The source side: filter output impedance

Looking back into the filter from the converter's input terminals, $Z_o$ is the inductor branch in parallel with the capacitor branch. It peaks at the filter resonance:

$f_0 = \frac{1}{2\pi\sqrt{L_f C_f}} \approx 10.7 \text{ kHz}, \qquad Z_0 = \sqrt{\frac{L_f}{C_f}} \approx 0.67\,\Omega$

A characteristic impedance of 0.67Ω sounds harmless next to a 20Ω load, until you account for the Q. With only 13mΩ of total series resistance, $Q \approx Z_0/R \approx 52$, and the impedance peak reaches 35Ω. Ceramic capacitors are the villain here: their near-zero ESR is exactly what you want for ripple and exactly what you don't want for damping.

The load side: converter input impedance

Within its loop bandwidth the buck presents $R_N \approx -20\,\Omega$. Above the bandwidth the loop stops defending constant power and the input impedance transitions towards the open-loop input impedance of the power stage. For a buck this is dominated by the inductor reflected through the duty ratio, $L/D^2 \approx 4.7\,\mu\text{H}/0.043 \approx 108\,\mu\text{H}$. A useful first-order model for plotting is $Z_{in} \approx -R_N + sL/D^2$: flat at $|R_N|$, then rising inductively. (For the full derivation of closed-loop input impedance, TI's SLVA662 is a good reference [2].)

The collision

Fig. 4 overlays the curves. The undamped filter peak at 10.7 kHz punches straight through the converter's $|Z_{in}|$: a clear criterion violation.

Fig. 4. Filter $|Z_o|$ against buck $|Z_{in}|$ (black). Undamped (red), the Q of 52 drives the 10.7 kHz resonant peak to 35Ω, through the converter's 20Ω negative-resistance plateau. With the $R_d$–$C_d$ branch fitted (teal), the peak falls to 0.7Ω, nearly 30 dB clear.

The Nyquist plot of $T_m$ (Fig. 5) confirms it: the undamped locus swings out past $-1$.

Fig. 5. Nyquist plot of $T_m = Z_o / Z_{in}$. The undamped locus (red) encircles $-1$: the interconnection is unstable even though filter and converter are each stable alone. Damped (teal), the locus collapses to a small loop near the origin, deep inside the Fig. 2 disc.

The fix: a damping snubber

The remedy is a damping network, an RC or RL snubber placed across one of the filter elements. (Not to be confused with the switch-node RC snubber inside the converter, which tames ringing on switching parasitics and does nothing for interface stability.) There are three standard placements [3], and the choice is a genuine trade-off rather than a matter of taste.

Option 1: $R_d$–$C_d$ across the filter capacitor. The most common choice and my default. The design rules of thumb:

• $C_d \approx 4 \times C_f$. The damping capacitor must dominate at resonance so that $R_d$ actually appears across the tank. Here: 100µF.
• $R_d \approx Z_0 = \sqrt{L_f/C_f}$. The optimum damping resistance is near the characteristic impedance. Here: 0.68Ω.

No DC current flows through the branch, so $R_d$ dissipates almost nothing. The cost is bulk: a capacitor four times the size of the one you already have. A convenient practical trick is that an aluminium electrolytic of the right value often supplies both $C_d$ and $R_d$ in one part, its ESR doing the damping. Check the ESR across temperature, though; it can triple at −40°C, and I'll come back to why that matters in the cascaded case. With the branch fitted, the peak drops from 35Ω to 0.7Ω (Fig. 4), and the Nyquist locus collapses to a small loop near the origin (Fig. 5).

Option 2: $R_p$ directly across the filter inductor. One resistor, no added capacitance. Attractive where bulk capacitance is constrained, by inrush limits or hot-swap requirements for example. The price is steep and often overlooked: above resonance, the noise current path runs through $R_p$ instead of being blocked by $L_f$, and the filter's attenuation slope degrades from −40 dB/decade to −20 dB/decade. In our example, an $R_p$ of 1.0Ω holds the $Z_o$ peak to 0.97Ω but gives up 30 dB of attenuation at 500 kHz (Fig. 6). If the filter exists to pass a conducted emissions limit, that 30 dB was the whole point of fitting it.

Option 3: $R_b$–$L_b$ in series, across the filter inductor. The blocking inductor $L_b$ restores the DC and high-frequency isolation that Option 2 gives away: at high frequency the parallel combination is still inductive ($L_f \parallel L_b$), so the −40 dB/decade slope survives, only shifted up slightly. With $L_b = L_f = 10\,\mu\text{H}$ and $R_b = 1.0\,\Omega$, the peak sits at 1.6Ω and the 500 kHz attenuation is within 6 dB of Option 1. The cost is a second inductor, which usually makes this the loser on price and board area against Option 1 unless capacitor volume is the binding constraint.

Fig. 6. The three placements compared. Top: all three hold $|Z_o|$ well below the converter's $|Z_{in}|$ (black), with peaks of 0.70Ω, 0.97Ω and 1.59Ω. Bottom: the price appears in the filter's attenuation. The $R_p$ option (amber) flattens to −20 dB/decade above resonance because noise bypasses $L_f$ through the resistor, giving up 30 dB at 500 kHz against the $R_d$–$C_d$ branch (teal). The $R_b$–$L_b$ option (blue) preserves the −40 dB/decade slope.

| Placement | Peak $|Z_o|$ (this example) | Attenuation at 500 kHz | Cost | |---|---|---|---| | (1) $R_d$–$C_d$ across $C_f$ | 0.70Ω | −67 dB | Bulk capacitance ($\approx 4C_f$) | | (2) $R_p$ across $L_f$ | 0.97Ω | −37 dB | One resistor; wrecks HF attenuation | | (3) $R_b$–$L_b$ across $L_f$ | 1.59Ω | −61 dB | Second inductor |

My ranking: Option 1 unless capacitance is genuinely constrained, then Option 3. Option 2 only where the filter isn't doing EMC duty, which in my experience is rare enough that I treat it as a last resort.

Cascaded stages: when the source is another converter

Now replace the passive filter with an active source: a 48V-to-12V voltage-mode bus converter feeding a 12V-to-1.0V / 20A point-of-load (POL) regulator (Fig. 7). Same criterion, but the character of $Z_o$ changes completely.

Fig. 7. The cascade. The bus converter (crossover 5 kHz, voltage mode) presents $Z_o$ at the intermediate bus; the POL (crossover 30 kHz) presents $Z_{in}$. The 220µF bulk capacitor (dashed) is the fix developed below.

The example system:

• Bus converter: $L = 15\,\mu\text{H}$, $C_{out} = 47\,\mu\text{F}$ (ESR 20mΩ), voltage-mode control, crossover $f_c$ = 5 kHz.
• POL: 20W output at 90% efficiency, so $P_{in} \approx 22$W and $R_N = 144/22 \approx -6.5\,\Omega$; crossover 30 kHz.

Where an active source's output impedance peaks

Below its crossover, the bus converter's feedback loop suppresses its output impedance: $Z_{o,CL} = Z_{o,OL}/(1+T)$, and $|1+T|$ is large. Above crossover, the loop is gone and $Z_o$ reverts to the passive output filter. The danger zone is the crossover region itself, where two effects conspire. Loop gain has fallen to unity so suppression is nearly finished, and in a voltage-mode design with modest phase margin, $|1+T|$ actually dips below one, amplifying the open-loop impedance rather than suppressing it.

In this example it's worse still, because the output filter resonance ($f_{res} = 1/2\pi\sqrt{LC} \approx 6$ kHz) lands almost on top of the 5 kHz crossover. The closed-loop $|Z_o|$ peaks at 13Ω at 6 kHz, twice the POL's 6.5Ω input impedance magnitude. Violation.

Note the contrast with the input-filter case: there the peak sat at a passive resonance you chose when you picked L and C; here it sits at the source converter's crossover, a frequency set by its compensation. This is why the common rule of thumb of separating the bandwidths of cascaded stages helps but is not sufficient on its own. Our POL crossover (30 kHz) is six times the bus converter's (5 kHz), and the system still fails, because the POL's negative-resistance region extends right down through the bus converter's crossover. Bandwidth separation controls where the interaction happens; it doesn't remove it.

The fix: damped intermediate bus capacitance

Adding bulk capacitance at the interface, electrically part of the bus converter's output, reshapes $Z_o$ in two ways. It pulls the output filter resonance below crossover, where the loop still has gain to suppress it, and its series resistance damps what remains. Here, a 220µF bulk capacitor with 50mΩ ESR drops the peak from 13Ω to 0.7Ω (Fig. 8).

Fig. 8. Bus converter $|Z_o|$ against POL $|Z_{in}|$ (black). With only 47µF of output capacitance (red), the filter resonance lands on the 5 kHz crossover and the closed-loop peak reaches 13Ω, through the POL's 6.5Ω plateau. With 220µF of damped bulk at the interface (teal), the resonance moves below crossover where loop gain still suppresses it, and the peak falls to 0.7Ω.

Be clear about what's doing the work: this is the same $R_d$–$C_d$ snubber as Option 1 above, with the capacitor's own ESR playing $R_d$. That framing exposes the weak point. ESR is not a controlled parameter. A typical aluminium electrolytic's ESR varies 3:1 or more from 25°C to −40°C and rises further as the part ages and dries out, so a design that has exactly enough damping at room temperature can be marginal at cold start in year five. And the failure can go the other way too: a well-meaning BOM substitution to an ultra-low-ESR polymer part removes the damping resistance entirely and leaves a residual peak the original design never had.

Where the design has to hold over a wide temperature range, or survive uncontrolled substitutions, fit the snubber deliberately: a low-ESR capacitor in series with a discrete damping resistor whose value you chose and toleranced, rather than a datasheet ESR you hoped for. The resistor costs pennies and turns the damping from an accident of construction into a design parameter. Whichever route you take, note the value in the schematic as a damping element so nobody "improves" it later.

One more caution: adding capacitance at its input changes the POL's own loop plant slightly. Re-check the POL's phase margin after the change, particularly if it senses input voltage for feedforward.

The distribution bus: one source, N loads

The distribution bus is where Middlebrook analysis most often gets skipped, and where the most counterintuitive failure lives: every source–load pair can pass the criterion individually while the aggregate system fails.

Fig. 9. The distribution bus: one 12V bus converter feeding four 25W POLs. The distribution inductances between the source's output capacitors and each load's terminals add to the $Z_o$ that load sees.

The example system: a 12V bus converter ($L = 10\,\mu\text{H}$, $C_{out} = 100\,\mu\text{F}$, ESR 25mΩ, $f_c$ = 5 kHz) feeds four identical 25W POLs at 90% efficiency.

Admittances add

Each POL presents:

$R_N = -\frac{12^2}{25/0.9} \approx -5.2\,\Omega$

But input admittances in parallel add, so the bus sees:

$Z_{in,agg} = \frac{Z_{in,1}}{N} \approx -1.3\,\Omega$

The bus converter's closed-loop $|Z_o|$ peaks at about 3.6Ω near its 5 kHz crossover. Against a single POL: 3.6Ω < 5.2Ω. Passes, with a little margin even. Against four: 3.6Ω > 1.3Ω, a broadband violation spanning nearly a decade (Fig. 10). A system integrator checking each rail-to-load pair in isolation would sign this off; the first full-system power-up would say otherwise.

Fig. 10. The aggregate trap. The bus converter's $|Z_o|$ (red, peak 3.6Ω) clears a single POL's $|Z_{in}|$ (solid black, 5.2Ω plateau) but not four in parallel (dashed black, 1.3Ω): admittances add, dropping the aggregate input impedance by N. The shaded band marks the violation.

Distribution parasitics make it worse

The wiring between source and loads is not free. Each nH of trace or harness inductance between the bus converter's output capacitors and a POL's input adds series impedance to the $Z_o$ that particular load sees, raising the source impedance at exactly the frequencies where the margin is thinnest and decoupling that load from the bulk capacitance that was supposed to protect it. On a compact PCB this is a dB or two; over a wiring harness it can dominate. The criterion must be evaluated at each load's terminals, with the interconnect impedance included on the source side.

Design approach: budget the admittance

For a bus, the clean method is to treat the criterion as an admittance budget:

1. Characterise (or specify) the bus converter's $|Z_o|$ including bulk capacitance and worst-case interconnect. If the damping relies on capacitor ESR, use the cold-temperature ESR here, for the reasons argued above.
2. Set the total allowed load admittance from the margin target: $|Y_{in,total}| \le 1/(2\,|Z_o|_{peak})$ for 6 dB.
3. Allocate that budget across loads, in proportion to power, since $|Y_{in}| \approx P_{in}/V_{bus}^2$ at low frequency.
4. Any new load added later must fit within the remaining budget, or the bus capacitance must grow to compensate.

That last point is the practical payoff: it turns "will adding this card destabilise the bus?" from a re-analysis exercise into a line item on an interface spec.

For this example, sweeping added bus capacitance against the worst-case margin (Fig. 11) shows the system crossing the criterion boundary at around 100µF and reaching a 6 dB margin at roughly 240µF of added bulk (30mΩ series resistance). The shape of the curve matters: steep at first, then flattening. Beyond a point, more capacitance buys little, because the residual peak is set by the damping resistance rather than by the resonant frequency.

Fig. 11. Worst-case margin, $\min_f 20\log_{10}(|Z_{in,agg}|/|Z_o|)$, against added bus capacitance with 30mΩ series resistance. The system crosses the criterion boundary near 100µF and reaches the 6 dB design margin at 237µF. The curve flattens because beyond that point the residual peak is set by the damping resistance, not the capacitance.

Measuring and simulating the impedances

The criterion is only as good as the two curves you compare.

Simulation. Both impedances come from AC injection at the interface. For $Z_o$: inject a small AC current into the source's output with the load replaced by its bias-point equivalent, and plot $V/I$. For $Z_{in}$: the same at the load's input. The detail that decides whether the result means anything is that the converter's $Z_{in}$ must be simulated closed loop, with an average model (or a SIMPLIS/periodic small-signal analysis) and the full compensator in place. The negative-resistance behaviour is a product of regulation. Simulate the power stage open loop, or with the output unregulated, and you'll see a benign positive impedance and conclude, wrongly, that there is nothing to worry about. This is probably the single most common way the analysis goes quietly wrong.

Bench. The interface impedances are measured with a frequency response analyser and an injection transformer (or a four-terminal impedance analyser at low power): break the connection, insert a small wideband injection resistor or transformer, sweep, and compute the impedance from the voltage and current at the interface (Fig. 12). Measure at the operating point. $R_N$ scales with $V_{in}^2/P_{in}$, so worst case is minimum input voltage at maximum load, and that's where the measurement and the design margin both matter most.

Fig. 12. AC injection at the interface. The same arrangement serves simulation and bench: perturb at the interface, measure voltage and current, and form $Z_o$ looking back or $Z_{in}$ looking forward. The load converter must be regulating during the measurement.

One criterion, three shapes of trouble

Scenario	What $Z_o$ looks like	What $Z_{in}$ looks like	Primary fix
Input filter	High-Q peak at the passive LC resonance	$-R_N$ flat, rising above loop bandwidth	Damping snubber: $R_d$–$C_d$ across $C_f$ by default; $R_b$–$L_b$ across $L_f$ if capacitance is constrained
Cascaded stages	Peak near the source converter's crossover, worst with voltage mode and low phase margin	Single load's $-R_N$	Damped bulk capacitance at the interface, with a controlled damping resistance rather than hoped-for ESR
Distribution bus	As the cascade, plus interconnect inductance seen per-load	$-R_N/N$: admittances add	Check against the parallel load impedance; budget admittance per load; size bus capacitance for margin

The discipline is the same in every case. Plot $|Z_o|$ and $|Z_{in}|$ on the same axes at the worst-case operating point and keep 6 dB of daylight between them. And remember that the load side gets lower every time someone adds a converter to the rail.

The plots in this article were generated from the component values quoted, using simplified closed-loop models ($Z_{in} \approx -R_N + sL/D^2$; $Z_{o,CL} = Z_{o,OL}/(1+T)$ with a first-order loop). They illustrate the mechanisms; for design sign-off, extract the impedances from your actual compensated models as described above. Doing that across a real system, with each converter's compensated small-signal model, the interface impedances overlaid automatically, and the damping components carried at their worst-case values over temperature rather than their room-temperature datasheet numbers, is exactly the analysis switchmode.io is being built to do. The impedance overlay is where the design conversation starts; the tolerance corners are where it gets signed off.

References

[1] R. D. Middlebrook, "Input Filter Considerations in Design and Application of Switching Regulators," IEEE Industry Applications Society Annual Meeting, 1976.

[2] Texas Instruments, "Demystifying Type II and Type III Compensators Using Op Amp and OTA for DC/DC Converters." [Online]. Available: https://www.ti.com/lit/an/slva662/slva662.pdf

[3] R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 3rd ed., Springer, 2020. Ch. 17 (input filter design and damping networks).